This application claims priority from Korean Patent Application Number 01-015643 filed Mar. 26, 2001, incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device including a control circuit for a delay locked loop (DLL).
2. Description of the Related Art
A DLL is included in a semiconductor memory device for the purpose of facilitating data transmission between the semiconductor memory device and a memory controller irrespective of the operation speed of the semiconductor memory device.
The DLL delays an external clock and generates an internal clock that is capable of driving a data output buffer. The data output buffer synchronizes output data with the rising edge or falling edge of the external clock responsive to the internal clock and then outputs the output data.
The DLL delays an externally input data strobe signal and synchronizes a phase of the data signal input into the data output buffer with respect to the phase of the data strobe signal. The DLL synchronization of the data signal with the data strobe signal optimizes data input setup/hold.
FIG. 1 is a block-diagram illustrating an analog DLL. Referring to FIG. 1, the conventional analog DLL includes a variable delay line (VDL) 1, a phase detector 3, a charge pump 5, and a compensation delay circuit 7.
The compensation delay circuit 7 outputs a feedback clock CLK_FB to the phase detector 3 in response to the internal clock CLK_INT externally supplied. The phase of the feedback clock CLK-FB leads the phase of an internal clock CLK_INT.
The phase detector 3 compares the phase of the feedback clock CLK_FB, the phase of which leads the phase of the internal clock CLK_INT with the phase of the external clock CLK_EXT and outputs a signal UP or DOWN responsive to the comparison.
The charge pump 5 outputs a control voltage Vcontrol for controlling the delay time of the VDL 1 responsive to the signal UP or DOWN output from the phase detector 3. The VDL 1 controls the delay time of the external clock CLK_ENT responsive to the control voltage Vcontrol of the charge pump 5.
Where the time when data is output is prior to receiving the external clock CLK_ENT, the VDL 1 increases the delay time. Conversely, where data is output after receiving the external clock CLK_ENT, the VDL 1 decreases the delay time. The DLL thus synchronizes and internal clock CLK_IN with the external clock CLK_ENT.
Accordingly, the DLL can always synchronize when data is output with the external clock CLK_ENT, irrespective of variations of power voltage or temperature.
When the DLL synchronizes the internal clock CLK_INT with the external clock CLK_EXT, the VDL 1, the phase detector 3, the compensation delay circuit 7, and the charge pump 5 all operate consuming a considerable amount of current.
When the DLL is turned off, the existing locking information is lost, and a considerable amount of time is required to lock the DLL. Accordingly, in a semiconductor memory device including the conventional DLL, the DLL is on in most operation modes. The DLL is turned off only in the self-refresh operation of a DRAM. In the latter case, the DLL is re-locked. Thus, even in a precharge mode where the DLL does not operate, a considerable amount of current (e.g., 10-20 mA) is consumed.
A data output strobe (not shown) is controlled by the internal clock CLK_INT that is generated with data output in the DLL. To output a preamble well, the DLL must generate a control signal in just three clock cycles immediately after receiving an active command. However, 200 clock cycles are required for locking the DLL that has previously been turned off. Thus, if the DLL is turned off when a semiconductor memory device operates in a precharge mode, it is impossible to output data in only three cycles immediately after the active command is input.
It is an object of the present invention to overcome the disadvantages associated with known semiconductor memory devices.
It is another object of the present invention to provide a semiconductor memory device capable of reducing current consumption of a DLL operating in a precharge mode.
Provided is a semiconductor memory device including a DLL adapted to generate an internal clock synchronized with an external clock responsive to a standby signal and a control signal generator adapted to output the standby signal responsive to a plurality of DLL control signals. The plurality of control signals includes a DLL reset, a DLL lock, a refresh mode, an address strobe, and a mode register signal.
The DLL comprises a phase detector adapted to generate a phase signal indicative of a phase difference between a phase of the external clock and a phase of the internal clock responsive to the standby signal, a charge pump adapted to generate a voltage control signal responsive to the standby signal and the phase signal, and a variable delay line (VDL) adapted to output the internal clock synchronized with the external clock responsive to the voltage control signal.
The control signal generator comprises a first logic circuit adapted to output a first signal to a DLL reset and refresh mode signals, a second logic circuit adapted to output a second signal responsive to an address strobe, an mode register, and a DLL lock signals, and a standby enabling circuit adapted to generate a standby enabling signal responsive to the first and second signals.
The first signal is active responsive to an active DLL reset signal and the second signal is active responsive to an active DLL lock signal.
The standby enabling circuit comprises a cross-coupled NOR circuit.
The phase detector is reset when the standby signal is active.
The variable delay line comprises at least one delay device and a delay time of the at least one delay device operates responsive to the voltage control signal.
The charge pump comprises a control voltage generator adapted to generate a current responsive to the phase signal.
Also provided is a DLL comprising an ON/OFF mode and a standby mode wherein the ON/OFF mode turns the DLL on or off and wherein the standby mode turns the DLL off while maintaining lock information responsive to a standby signal. The standby signal is enabled responsive to a standby enable signal and the standby enable signal is inactive when a DLL reset signal is active. The standby enable signal is active when a DLL lock signal is active.
If one of the DLLRESET and SELF_EXIT signals is activated, the standby enable signal STB_EN is deactivated. In this case, the DLL cannot operate in a standby mode even though the semiconductor memory device is in the precharge mode. In the standby mode, locking information stored before the precharge mode of the semiconductor memory device is maintained, and predetermined circuits included in the DLL do not operate.